1. Technical Field of the Invention
The present invention relates to integrated circuits and more particularly to MOS-type transistors.
2. Description of Related Art
The fabrication of transistors produced in MOS technology is faced with several problems, among which to be noted are short-channel effects.
Such is in particular the case in transistors produced on a bulk silicon substrate.
It will be recalled here that a short-channel, that is to say one having a distance (or length) that is very short between the source and the drain of the transistor, leads to a reduction in the threshold voltage of the transistor. This may in the extreme limit lead to a transistor being obtained that is very difficult to control.
Transistors produced in SOI (Silicon On Insulator) technology, in particular in fully-depleted SOI technology, apart from the advantages associated with the formation of a more compact architecture than in a bulk silicon substrate, make it possible to reduce the short-channel effects.
Using this technique, the substrate is made of silicon and is formed on top of a buried oxide (BOX) layer.
Now, in an SOI structure, the thickness of both the silicon film and the buried oxide layer is relatively small. This is because the buried oxide layer is generally between 1450 and 4000 Å. Such is also the case of the SOI film, the thickness of which is generally around 200 Å.
It has been found that the small thickness of the buried oxide layer reduces the electrostatic coupling between the drain region and the source region. This limits the phenomenon of short-channel effects.
During the etching operations carried out when producing the isolation region that defines the active zone, in which the transistor is defined, the buried oxide layer is liable to be etched. This results in an excessive consumption of insulation material for producing the STI (Shallow Trench Isolation) region.
In addition, it has also been found that, when using this technique, the SOI film protrudes on top of the buried oxide layer, so that the gate region is also formed laterally on either side of the SOI region, thereby tending to create parasitic transistors on the SOI sidewalls coated with the gate material.
There is accordingly a need in the art to alleviate the drawbacks of the techniques for fabricating MOS transistors produced in SOI technology.